1. Field of the Invention
This disclosure relates to a semiconductor memory device, and more particularly, to a command decoder and decoding method for use in a semiconductor memory device.
2. Description of Related Art
A command decoder for use in a double data rate synchronous dynamic random access memory (DDR SDRAM) device receives and decodes an inverted chip selecting signal CSB, an inverted row address strobe signal RASB, an inverted column address strobe signal CASB, and an inverted write enable signal WEB at a rising edge of a clock signal CLK to generate a mode setting command MRS, an active command ACTIVE, a pre-charge command PRECHARGE, a write command WRITE, a read command READ, and a refresh command REFRESH.
FIG. 1 is a timing diagram illustrating an operation of a conventional command decoder for use in a DDR SDRAM device.
When an inverted chip selecting signal CSB having a logic “low” level, an inverted row address strobe signal RASB having a logic “low” level, an inverted column address strobe signal CASB having a logic “low” level, and an inverted write enable signal WEB having a logic “low” level are applied externally at a rising edge of a clock signal CLK, a command decoder internally generates a mode setting command MRS.
When the inverted chip selecting signal CSB having a logic “low” level, the inverted row address strobe signal RASB having a logic “low” level, an inverted column address strobe signal CASB having a logic “high” level, and the inverted write enable signal WEB having a logic “high” level are applied externally at a rising edge of the clock signal CLK, the command decoder generates an active command ACTIVE internally.
When the inverted chip selecting signal CSB having a logic “low” level, the inverted row address strobe signal RASB having a logic “low” level, the inverted column address strobe signal CASB having a logic “high” level, and the inverted write enable signal WEB having a logic “low” level are applied externally at a rising edge of a clock signal CLK, the command decoder internally generates a pre-charge command PRECHARGE.
When the inverted chip selecting signal CSB having a logic “low” level, the inverted row address strobe signal RASB having a logic “high” level, the inverted column address strobe signal CASB having a logic “low” level, and the inverted write enable signal WEB having a logic “low” level are applied externally at a rising edge of a clock signal CLK, the command decoder internally generates a write command WRITE.
When the inverted chip selecting signal CSB having a logic “low” level, the inverted row address strobe signal RASB having a logic “high” level, the inverted column address strobe signal CASB having a logic “low” level, and the inverted write enable signal WEB having a logic “high” level are applied externally at a rising edge of a clock signal CLK, the command decoder internally generates a read command READ.
When the inverted chip selecting signal CSB having a logic “low” level, the inverted row address strobe signal RASB having a logic “low” level, the inverted column address strobe signal CASB having a logic “low” level, and the inverted write enable signal WEB having a logic “high” level are applied externally at a rising edge of a clock signal CLK, the command decoder internally generates a refresh command REFRESH.
Table 1 shows a generation of internal command signals MRS, ACTIVE, PRECHARGE, WRITE, READ, and REFRESH according to a state of external command signals CLK, CSB, RASB, CASB, and WEB of the conventional DDR SDRAM device.
TABLE 1InternalcommandExternalCommandMRSACTIVEPRECHARGEWRITEREADREFRESHCSBLLLLLLRASBLLLHHLCASBLHHLLLWEBLHLLHH
In Table 1, “L” denotes a logic “low” level, and “H” denotes a logic “high” level
Accordingly, the command decoder for use in the conventional DDR SDRAM device has a simple circuit configuration.
A command decoder for use in a fast cycle random access memory (FCRAM) device receives and decodes an inverted chip selecting signal CSB and a signal FN for two cycles to generate a mode setting signal MRS, a read command READ, a write command WRITE, and a refresh command REFRESH.
FIG. 2 is a timing diagram illustrating an operation of a command decoder for use in a conventional FCRAM device.
When a read command RDA including an inverted chip selecting signal CSB having a logic “low” level and a signal FN having a logic “high” level is applied at a rising edge of a first clock signal CLK and a mode setting signal MRS including the inverted chip selecting signal CSB having a logic “low” level are applied at a rising edge of a second clock signal CLK, a command decoder generates a mode setting signal MRS.
When the read command RDA is applied at a rising edge of a first clock signal CLK and a lower address latch command LAL including the inverted chip selecting signal CSB having a logic “high” level is applied at a rising edge of a second clock signal CLK, the command decoder generates a read command READ.
When a write command WRA including the inverted chip selecting signal CSB having a logic “low” level and the signal FN having a logic “low” level is applied at a rising edge of a first clock signal CLK and a refresh command REF including the inverted chip selecting signal CSB having a logic “low” level is applied at a rising edge of a second clock signal CLK, the command decoder generates a refresh command REFRESH.
When the write command WRA is applied at a rising edge of a first clock signal CLK and the lower address latch command LAL is applied at a rising edge of a second clock signal CLK, the command decoder generates a write command WRITE.
Table 2 shows a generation of internal command signals MRS, WRITE, READ, and REFRESH according to a state of external command signals CLK, CSB, and FN (RDA, MRS, WRA, LAL) of the conventional DDR SDRAM device.
TABLE 2InternalCommandMRSREADREFRESHWRITEExternalFirstSecondFirstSecondFirstSecondFirstSecondcommandRDAMRSRDALALWRALALWRALALCSBLLLHLLLHFNHXHXLXLX
In Table 2, “L” denotes a logic “low” level, “H” denotes a logic “high” level, and “X” denotes a “don't care”.
As described above, command decoders of the DDR SDRAM device and the FCRAM device have different decoding methods and different circuit configurations.
Recently, development has begun on a semiconductor memory device that can operate as both a DDR SDRAM device and a FCRAM device. However, as described above, the command decoders work completely differenctly.